expert · ordering

Works on x86, Breaks on ARM

A lock-free structure works reliably on x86-64 and fails intermittently on AArch64. What class of bug is this, and how do you reason about it?

Practical scenario

A queue used in production on x86 for two years fails a soak test within minutes on new ARM-based instances. The team suspects a compiler bug.

What it tests

• Understanding that hardware memory models differ in strength
• Whether the candidate reasons from the language model rather than the chip
• Recognition that "works on x86" is not evidence of correctness

Lessons behind this question

Hardware Memory Models Are Not Language Memory Models Why Your Loads and Stores Happen Out of Order Memory Barriers: Ordering, Not Flushing Store Buffers: Where Your Writes Wait Sequential Consistency: The Model You Already Have Atomic Instructions: What the Hardware Actually Guarantees